The present invention relates to a semiconductor device which is well suited for application to a semiconductor memory device such as a ROM (Read Only Memory), and more particularly to a semiconductor memory device which achieves a higher packing density or an increased memory capacity by employing MOSFETs (MOS type field effect transistors) as its elements, and a method of manufacturing the same.
In general, semiconductor devices such as an IC and LSI have had enhancements in the packing density and the operating speed promoted more and more in recent years. Such progress in semiconductor devices is much indebted to the advancements of micro-processing techniques among the manufacturing techniques of the semiconductor devices. For example, in a semiconductor device whose circuit elements are MOSFETs, the working dimension of a gate electrode is often used as the representative of the micro-processing level of the whole semiconductor device. In addition, when the gate electrode length or the channel length is designed to be smaller, a device of higher integration can be constructed. By shortening the channel length, the "on" resistance of the MOSFET can be lowered. Also, for designing an IC of high speed, it is important to shorten the channel length.
However, when the channel length is shortened, the so-called short channel effect arises. The dependence of the threshold voltage (V.sub.th) upon the channel length poses a problem. In order to cope with this, a countermeasure such as shallower source and drain regions is required.
On the other hand, photolithography is usually used for the formation of the gate electrodes, etc. Problems in this technique, such as the mask registration precision, and the developing and etching precisions, limit the microminiaturization of a pattern. Also, in forming the gate electrodes, it is very difficult to finely work the channel lengths at high precision. Consequently, the proper adjustment of the threshold voltage (V.sub.th) becomes difficult.
A conventional MOS structure is such that wiring layers are formed on a semiconductor substrate in a stacked state. With the multilayering of wiring, the wiring layer on the upper side of a device is not as flat as desired, e.g., undesirably has steps. For this reason, drawbacks such as the disconnection and short-circuit of the upper layer wiring are liable to occur. Especially in a semiconductor memory device such as a ROM which needs a plurality of (a large number of) wiring leads in each of vertical and lateral directions in plan, the drawbacks of this sort are prone to occur conspicuously.